This invention relates generally to analog-to-digital converters, and in particular to a multiple-slope integrating analog-to-digital converter having improved accuracy and resolution.
Conventional dual-slope integrating analog-to-digital converters (ADCs) are well known to those skilled in the art, and operate by placing a charge on a capacitor associated with an operational amplifier integrator proportional to an unknown voltage to be measured (charging the capacitor for a predetermined period of time, resulting in the first slope of the dual-slope system), applying a reference voltage to discharge the integrator capacitor at a known rate (resulting in the second slope) and measuring the amount of time for discharge, and finally calculating the unknown voltage as a ratio of the measured time and the predetermined time multiplied by the reference voltage.
Because of the long time periods and perhaps relatively high voltage headroom required to charge and discharge in the integrator capacitor in high resolution ADC systems, multiple slope integrating ADCs were devised which periodically remove or add known quantities of charge (represented by slopes of known polarity and duration) during the integrate, or charge cycle (also known as the run-up cycle) so that an unknown input voltage is never large enough to saturate the integrator, and a relatively small charge remains on the integrating capacitor to be discharged during the de-integrate, or discharge cycle (also known as the run-down cycle). The charge removed or added during the integrate cycle is kept track of by counting slopes which represent the known quantities of charge removed or added, and accounted for in making the final determination of the value of the unknown voltage. The multiple slope techniques may also be applied during the de-integrate or run-down cycle to shorten the amount of time required to discharge the integrator capacitor, resulting an ADC with increased sensitivity and speed. An example of a multiple slope integrating ADC is taught in U.S. Pat. No. 4,357,600 to Ressemeyer et al.
Many of the problems associated with prior art multiple slope integrating ADCs stem from the large number of high-speed switching operations that occur in a short period of time, particularly during the integrate cycle. For example, mismatches in the physical characteristics of the switches themselves, however slight, will result in timing errors that will add up over the course of two thousand switching operations. Mismatches in reference currents, rectification of cross coupling of switch control signals which pumps extraneous current into the integrator summing node, and switch charge injection which also delivers unwanted current into the integrator summing node all result in non-linear errors, offset, and scale factor errors which cumulatively degrade measurement accuracy. These errors are very critical in analog-to-digital converters with 51/2 or 61/2 digits of resolution. The errors are significantly worse when standard components such as off-the-shelf analog switches are used for the input switching circuits. Prior art investigators have attempted to overcome these problems by implementing the input switching circuits in application-specific integrated circuit form and tightly controlling the manufacturing process, leading to very expensive solutions.
Another problem associated with prior art multiple slope integrating ADCs is what is known as the "toning" effect, or fixed pattern that occurs with the integrator after many, many switching operations in which the switching sequence is always the same. As an example, for input voltages near zero volts, a small change in input voltage may result in a larger than expected change in the measured output due to a change in the pattern. This error is referred to as differential non-linearity.